`timescale 1ns/1ns

module mul_addtree(mul_a, mul_b, mul_out);
input [3:0] mul_a, mul_b; //IO 端口声明
output [7:0] mul_out;
wire [7:0] mul_out; //连线类型声明
wire [7:0] stored0, stored1, stored2, stored3;
wire [7:0] add01, add23;

//逻辑设计
assign stored3 = (mul_b[3]) ? (mul_a << 3) : 8'b0;
assign stored2 = (mul_b[2]) ? (mul_a << 2) : 8'b0;
assign stored1 = (mul_b[1]) ? (mul_a << 1) : 8'b0;
assign stored0 = (mul_b[0]) ? (mul_a << 0) : 8'b0;
assign add01 = stored0 + stored1;
assign add23 = stored2 + stored3;
assign mul_out = add01 + add23;

endmodule

///////////测试代码
module mult_addtree_tb;

reg [3:0]mult_a;
reg [3:0]mult_b;
wire [7:0]mult_out;

mul_addtree U1(.mul_a(mult_a), .mul_b(mult_b), .mul_out(mult_out));

initial begin //测试信号 
    mult_a = 0;
    mult_b = 0;
    repeat(9) begin
        #20 mult_a = mult_a+1;
        mult_b = mult_b+1;
    end
end

initial begin
    $dumpfile("mult_addtree_tb.vcd"); //生成的 vcd 文件名称
    $dumpvars(0, mult_addtree_tb); //测试模块名称
    #200 $finish;
end

endmodule